1. Field of the Invention
The present invention relates to a semiconductor device and a signal processing method, and in particular those preferably adoptable to a semiconductor device having an interface relevant to a double-data-rate (DDR) synchronous dynamic random access memory (SDRAM).
2. Description of the Related Art
In circuit design of memory controller corresponded to DDR-SDRAM, DDR2-SDRAM and so forth, particular difficulties reside in a section allowing an internal flipflop to capture read data output from a memory, and a section taking part in synchronizing an output from the flipflop with a system clock. In determination of a valid range of data to be synchronized, it is important to calculate a round-trip delay which represents a length of time ranging from output of a clock from a memory controller, via travel through a memory (SDRAM), up to return of the clock as a data strobe signal DQS back to the memory controller. A timing design therefor, however, needs simulation and verification with an accuracy of several tens to several hundreds of picoseconds, and therefore needs an extremely long time for delay design of the memory controller and timing design of printed circuit board (PCB).
Memory element connected to the memory controller, quantity and types of DIMM modules, constitutional materials and number of layers of the printed circuit board are far from being unconditionally determined. Moreover, recent trends in DDR-SDRAM and DDR2-SDRAM are characterized by increased data rate evolving from DDR200, 266, 333 to 400, and from DDR2 400, 533 to 667. It is therefore difficult to simulate and verify every feasible memory-mounted configurations, over the entire regions covering all variations in the manufacturing and temperature conditions.
As for the memory controller for DDR-SDRAM, there has been proposed a method of adjusting timing by providing a capacitance corresponded to a memory element on a line simulating an actual PCB transmission path (printed wiring), actually reading the memory based on a dummy reading cycle, measuring the response waveform, and adjusting the phase of the data strobe signal DQS (see Patent Document 1, for example).
Patent Document 2 describes a technique of suppressing reflection of signals on a transmission line, ascribable to discontinuity or mismatching of characteristic impedance, and associated ringing.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2005-78547
[Patent Document 2] Japanese Patent Application Laid-Open No. 2001-183422
The method described in Patent Document 1 adds a PCB line simulating an actual transmission path, and provides only a load capacitance as the load. The load capacitance connected via the transmission path is, therefore, largely restricted depending on which of a directly-coupled DRAM or a DTMM module is used, quantity of DRAM, rank of the DIMM module, number of components of the DIMM module and so forth, so that disagreement of as much as several tens to several thousands of picoseconds in delay may occur between such simulative transmission path simply having the load only and the actual transmission path.
The method is also disadvantageous in that it does not use an actual data strobe signal or a clock signal, and therefore does not conform to a geometry of an actual transmission path, so that flight times of the data strobe signal and the clock signal cannot be measured. Adoption of the dummy read cycle load undesirably complicates the design of the memory controller-related components, and actual circuit operation cannot be bested unless the memory is connected.